1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor storage device testing method and, more particularly, to a semiconductor device having an internal power supply voltage generation circuit and a method of testing a semiconductor storage device having a spare memory cell.
2. Description of the Background Art
For such a semiconductor memory as a dynamic random access memory (hereinafter referred to as DRAM), it is a conventional practice to conduct two stages of tests, a wafer test and a final test.
In the wafer test, with numerous memory chips formed on a semiconductor wafer and a test probe made in contact with a pad of each memory chip, a test is performed to determine whether each memory cell of each memory chip is normal or not under predetermined wafer test conditions. On a remediable memory chip, a defective memory cell row or column is replaced by a spare memory cell row or column by selectively cutting off a group of fuses on the chip. In addition, by selectively cutting off another group of fuses on the chip, tuning of an internal power supply potential intVCC is conducted.
Next, a normal memory chip and a remedied memory chip are cut out from the semiconductor wafer and incorporated into a package to make a DRAM product. In the final test, with each DRAM product mounted on a test board, a test is performed to determine whether each memory cell of each DRAM product is normal or not under predetermined final test conditions. Normal DRAM products are shipped, while DRAM products having a newly found defective memory cell are subjected to an analysis of a defective mode.
Difference in results of a wafer test and a final test derives from different test conditions. While in a wafer test, with a test probe attached to a pad of each DRAM chip, a simple test is performed, a final test is conducted with each DRAM product mounted on a test board under conditions severer than conditions of actual use. Since it is desirable that results of the wafer test and the final test coincide with other, it is a conventional practice to analyze the results of the final test and feed back the analysis results into wafer test conditions.
With respect to defective DRAM products, however, since laser trimming of a fuse is already conducted and cut off fuses can not be restored, defective DRAM products can not be precisely analyzed.
More specifically, since before and after the tuning of an internal power supply potential intVCC, the internal power supply potential intVCC has a potential change of 0.1 to 0.4V, even if new voltage conditions for a wafer test are obtained by analyzing a defective DRAM product, the conditions are in many cases inappropriate.
In addition, since a defective memory cell row or column is replaced by a spare memory cell row or column, it is impossible to detect how many defective memory cells exist in the replaced memory cell row or column even by testing a defective DRAM product under various wafer test conditions and accordingly impossible to conduct accurate analyses.
An object of the present invention is to provide a semiconductor device and a semiconductor storage device testing method enabling review of wafer test conditions to be executed appropriately in a short time period.
The semiconductor device according to the present invention is provided with an internal power supply voltage generation circuit for generating an internal power supply voltage based on an external power supply voltage, at least one first fuse coupled to the internal power supply voltage generation circuit for adjusting a level of the internal power supply voltage, a first switching element connected in parallel to the at least one first fuse and responsive to an instruction of an initial state return mode to become conductive for returning the level of the internal power supply voltage to an initial value, and an internal circuit driven by the internal power supply voltage. Therefore, even when after the first fuse is cut off to conduct a final test, a defective part is newly detected in the internal circuit, the device can be returned to a state at a wafer test by rendering the first switching element conductive, so that wafer test conditions can be appropriately reviewed in a short time period.
The internal power supply voltage generation circuit preferably includes a constant-current source for outputting a predetermined constant current and a plurality of resistance elements connected in series between an output node of the constant-current source and a line of a reference potential, to any of which plurality of resistance elements, the at least one fuse is connected in parallel. In this case, cutting off the fuse results in increasing a value of a resistance between the output node and the reference potential line to increase the internal power supply voltage.
Also preferably, the semiconductor device is a semiconductor storage device and the internal circuit includes a plurality of memory cells, a spare memory cell for replacing a defective memory cell, a decoder provided corresponding to each memory cell and responsive to application of an address signal assigned to a corresponding memory cell for activating the corresponding memory cell, and at least one second fuse for programming an address signal assigned to a defective memory cell, and includes a redundant decoder responsive to application of a programmed address signal for inactivating the decoder, as well activating the spare memory cell, a second switching element connected in parallel to the at least one second fuse and responsive to an instruction of the initial state return mode to become conductive for temporarily erasing a programmed address signal, and a write/read circuit for writing/reading data to/from memory cells activated by the decoder and the redundant decoder. In this case, since even when after the first and the second fuses are cut off to conduct the final test, a defective memory cell is newly detected, the device can be returned to a state at the wafer test by rendering the first and the second switching elements conductive, wafer test conditions can be reviewed appropriately in a short time period.
In a method of testing a semiconductor storage device according to the present invention, the semiconductor storage device includes a plurality of memory cells, a spare memory cell for replacing a defective memory cell, a decoder provided corresponding to each memory cell and responsive to application of an address signal assigned to a corresponding memory cell for activating the corresponding memory cell, and at least one first fuse for programming an address signal assigned to a defective memory cell, and includes a redundant decoder responsive to application of a programmed address signal for inactivating the decoder, as well activating the spare memory, a first switching element connected in parallel to the at least one first fuse and responsive to an instruction of the initial state return mode to become conductive for temporarily erasing a programmed address signal, and a write/read circuit for writing/reading data to/from memory cells activated by the decoder and the redundant decoder. Then, with the semiconductor storage device formed on a semiconductor wafer, a test is performed to determine whether each memory cell is normal or not under first test conditions and when a defective memory cell is detected, the at least one first fuse is cut off to replace the defective memory cell by the spare memory cell. Next, the semiconductor storage device is cut out from the semiconductor wafer and accommodated in a package and with the device accommodated, a test is performed to determine whether each memory cell is normal or not under second test conditions and when a defective memory cell is newly detected, the initial state return mode is instructed to render the first switching element conductive to review the first test conditions. Accordingly, even when after the first fuse is cut off to conduct the final test, a defective memory cell is newly detected, the device can be returned to a state at the wafer test by rendering the first switching element conductive, so that the first test conditions, that is, wafer test conditions can be reviewed appropriately in a short time period.
Preferably, the semiconductor storage device further includes an internal power supply voltage generation circuit for generating an internal power supply voltage for driving the decoder, the redundant decoder and the write/read circuit based on an external power supply voltage, at least one second fuse coupled to the internal power supply voltage generation circuit for adjusting a level of the internal power supply voltage and a second switching element connected in parallel to the at least one second fuse and responsive to an instruction of the initial state return mode to become conductive for returning the level of the internal power supply voltage to an initial value. Then, at the time when the at least one first fuse is cut off, the at least one second fuse is also cut off and at the time when the first switching element is rendered conductive, the second switching element is also rendered conductive. In this case, since even when after the first and the second fuses are cut off to conduct the final test, a defective memory cell is newly detected, the device can be returned to a state at the wafer test by rendering the first and the second switching elements conductive, the first test conditions, that is, wafer test conditions, can be appropriately reviewed in a short time period.